`timescale 1ns/1ns
module buffer_tb;
parameter WIDTH = 8;
	reg 	      	clk;
    	reg           	rst_n;
    	reg 	      	in_wr;
    	reg	[WIDTH-1:0] in_wdata;
    	reg 	        in_rd;
    	wire  	[WIDTH-1:0] out_rdata;
    	wire            out_empty;
    	wire            out_full;

defparam buffer.WIDTH = 8;
defparam buffer.PSIZE = 2;
TOP	buffer(
.clk(clk),
.rst_n(rst_n),
.in_wr(in_wr),
.in_wdata(in_wdata),
.in_rd(in_rd),
.out_rdata(out_rdata),
.out_empty(out_empty),
.out_full(out_full)
);

initial begin 
	clk = 0;
	rst_n = 0;

	#100
	rst_n = 1;
	
	#100
	in_wr = 1;
	in_rd = 0;
	in_wdata = 10;

	#100
	in_wr = 0;
	in_rd = 1;

	#100
	in_wr = 1;
	in_rd = 0;
	in_wdata = 11;
	
	#100
	in_wr = 1;
	in_rd = 0;
	in_wdata = 12;
	
	#100
	in_wr = 0;
	in_rd = 1;

	#100

	#100
	$stop;
end

always #50 clk = ~clk;
endmodule
